The present invention relates to peripheral storage devices and, more particularly, to a multi-function buffer system for use in a peripheral storage device.
Hard disk drives and other peripheral storage devices have become a standard feature in most computer systems. Such devices provide mass storage functionality for a host computer, and may include hard disk drives, CDROM drives, tape drives, optical disk memory devices, floppy disk drives, and the like. For example, hard disk drives include one or more magnetically coated platters used for storing program instructions, data, and other information used by the computer system. One or more such platters may be configured in a stack, which may be rotated by a spindle or servo motor. A space is provided between each platter to allow an arm having a read/write head to be positioned on each side of each platter such that information may be stored and retrieved. Information may be stored on one or both sides of the platters, which are generally organized into sectors, tracks, zones, and cylinders.
The read/write heads may be mounted onto one or more suspension arms whereby each of the read/write heads may be positioned as desired. The suspension arms may be coupled together at a voice coil motor (VCM) to form one unit or assembly that is positionable by the voice coil motor. The voice coil motor positions the suspension arms so that an active read/write head is properly positioned for reading or writing information. The read/write heads may thus be positioned between an inner diameter and an outer diameter of the platters in a controlled fashion to access data stored thereon.
Hard disk drives and other types of peripheral storage devices also include a variety of electronic control circuitry for processing data and for controlling its overall operation, including a hard disk controller. For example, the controller may include a processor, a pre-amplifier, a read channel, a write channel, a servo controller, a motor control circuit, a read-only memory (ROM), a random-access memory (RAM), and a variety of disk control circuitry to control the operation of the hard disk drive and to properly interface the hard disk drive to a bus in a host computer system. The disk control circuitry generally includes a processor (e.g., a DSP, microprocessor, microcontroller, or the like) for executing instructions stored in memory to control the operation and interface of the hard disk drive.
Hard disk drives and other peripheral storage devices perform write, read, and servo operations when storing and retrieving data. Generally, a write operation includes receiving data from a system bus and storing the data on the platters. In a read operation, the appropriate sector to be read is located and data that has been previously written to one or more platters is read. The data is then provided to the host computer system. The disk drive may further comprise some form of buffer memory to buffer or temporarily store information on its way from the host system to the storage media (platters) and/or on its way from the media to the host system. In addition, the control circuitry may include instruction memory (e.g., ROM, EEPROM, FLASH, and the like) used for storing firmware instructions for execution by the controller processor, and execution memory (e.g., SRAM) used for storing temporary variables, intermediate results, and the like (scratchpad).
Sometimes, buffer memory is used to store executable instructions as well as to buffer transferred data. For instance, the buffer memory may be used to store updated firmware, which may be executed by the controller processor while the instruction memory is rewritten to include the updated firmware instructions. Thereafter, the controller processor may execute normally by fetching the updated firmware instructions from the instruction memory, whereby the buffer memory is again free for other usage as a buffer for transferred information.
Such buffer memory has heretofore primarily been external to the peripheral storage device controller. The controller accesses the external buffer memory via a buffer manager in the controller circuit. Whereas the primary purpose of such buffer memory is for temporary storage of information in transit to or from the platters, firmware instructions are commonly stored in the buffer, for instance, those instructions associated with small and/or low speed functions.
Peripheral storage devices, such as disk drive products are desired for a variety of different applications, each having different performance requirements. For instance, some disk drive applications are cost sensitive, and may sacrifice performance (e.g., by providing only a small amount of processor RAM) in favor of reduced cost, while providing an integral buffer memory for temporary storage of information being transferred. Other less cost sensitive applications may require a large amount of buffer memory (e.g., beyond the amount which may be easily integrated into the controller circuitry), as well as more processor instruction execution RAM. The high performance applications may tend to use a buffer RAM sufficiently large as to make integration not cost-effective when discrete or external RAM options are less expensive.
Peripheral storage device manufacturers accordingly have made efforts to keep product costs low and at the same time to maximize product performance, across product lines with offerings for a variety of cost/performance goals. However, some tradeoffs are inevitable. For example, integration of memory into a controller circuit may provide improved access time performance, but may increase the cost compared with external memory devices. While such tradeoffs may be made on a product-by-product basis, further cost reduction across an entire product line may be realized through the provision of components common to two or more peripheral storage device products, each of which has different cost/performance design goals. Thus, there is a need for improved peripheral storage device controller circuits providing reduced cost across a product line of drive controllers having diverse performance/cost design goals.
The present invention provides a multi-function buffer system comprising an integrated memory, which may be adapted for use as instruction memory, scratchpad RAM, and/or as an information buffer. For instance, the integrated memory may be employed by a processor for storage of instructions (e.g., instruction space) and/or data (e.g., data space or xe2x80x98scratchpadxe2x80x99 memory). Alternatively or in combination, the integrated memory may be employed by a buffer manager to buffer or store information being transferred between a peripheral storage device and a host computer. The multi-function memory may thus be employed in both low and high performance peripheral storage devices, allowing reduced cost across multiple product offerings. The buffer system may provide interfacing from the integrated memory to the controller buffer manager or to a processor. Thus, the buffer system may be employed to provide buffer memory via the buffer manager in cost sensitive peripheral storage devices.
Additional interfacing may be provided to an external buffer memory. Where an external buffer memory is provided in the peripheral storage device, the buffer system may provide access between the external buffer memory and the buffer manager, while also providing access between the processor and the internal memory. For high performance peripheral storage devices, therefore, the buffer system allows use of a large external buffer memory via the buffer manager, as well as the addition of processor execution memory for scratchpad or instruction storage use via the processor. Thus, the invention provides a versatile buffer system adaptable to various applications having diverse and/or disparate performance goals and requirements, while achieving lower cost associated with universally applicable components.
The selective access to the internal memory device, as well as the access to the external buffer memory device may be provided by an access control device in the buffer system. The control device may be configured to provide electrical communication between the internal memory device and one of the processor and the buffer manager. For instance, where no external buffer memory exists in the peripheral storage device system, the control device may provide access between the internal memory and the buffer manager, whereby buffer memory is provided to the peripheral storage device. The invention further contemplates a peripheral storage device system, as well as a methodology for providing buffer memory in a peripheral storage device system.
One aspect of the invention provides a peripheral storage device buffer system, comprising a memory device and a control circuit or device. The buffer system may be electrically connected or associated with a processor and a buffer manager associated with a peripheral storage device system. The control circuit selectively provides access with the memory device to the buffer manager and/or the processor. In this way, the buffer system may be used in a variety of situations for peripheral storage device systems having various cost and/or performance goals.
According to another aspect of the invention, the buffer system may be employed as an interface to a second memory device, such as an external buffer memory. The control circuit may connect the first memory device with the processor and connect the second memory device with the buffer manager according to a control state. For instance, if the second memory device is present in the peripheral storage device system, the second memory device may employed as buffer memory accessible by the peripheral storage device buffer manager, with the first memory device acting as processor execution memory for scratchpad and/or instruction storage purposes. If no second memory device is present, the control circuit may connect the first memory device with the buffer manager to act as buffer memory.
According to still another aspect of the invention, a peripheral storage device system is provided having a peripheral storage device, a controller, a processor, and a peripheral storage device buffer system. The buffer system comprises a first memory device and a control circuit adapted to selectively provide electrical communication between the first memory device and one of a buffer manager and the processor. The peripheral storage device system may further comprise a second memory device in electrical communication with the buffer system. In this case, the buffer system control circuit may provide electrical communication between the first memory device and the processor, and between the second memory device and the buffer manager.
According to yet another aspect of the invention, a method is provided for providing buffer memory in a peripheral storage device system. The method comprises connecting a buffer system with a buffer manager and a processor associated with the peripheral storage device system, wherein the buffer system includes a first memory device and a control device with a control state associated therewith. The method further comprises providing electrical communication between the first memory device and the processor using the control device if the control state is in a first state, and providing electrical communication between the first memory device and the buffer manager using the control device if the control state is in a second state. In addition, the method may comprise selectively providing electrical communication between a second memory device associated with the peripheral storage device system and the buffer manager using the control device if the control state is in the first state.